Proceedings, Seventh annual IEEE Symposium on Field-Programmable Custom Computing Machines : FCCM'99 : April 21-23, 1999, Napa Valley, California /

Proceedings, Seventh annual IEEE Symposium on Field-Programmable Custom Computing Machines : FCCM'99 : April 21-23, 1999, Napa Valley, California /

Show other versions (31)
Bibliographic Details
Corporate Authors: IEEE Symposium on FPGAs for Custom Computing Machines Napa Valley, Calif., IEEE Computer Society Technical Committee on Computer Architecture
Other Authors: Arnold, Jeffrey M, Pocek, Kenneth L
Format: Conference Proceeding Book
Language:English
Published: Los Alamitos, Calif. : IEEE Computer Society, c1999
Subjects:
Computer engineering > Congresses
Field programmable gate arrays > Congresses
Computer engineering
Field programmable gate arrays
Conference papers and proceedings
LEADER 08704nam a22005054a 4500
001 945072af-391f-486f-9a60-55f7a1e9d460
005 20240421000000.0
008 971021s1999 caua b 101 0 eng c
020 |a 0769503756 
035 |a (MdBJ)2103964 
035 |a (NIC)notisASA8275 
035 |a (OCoLC)42950440 
035 |a 2103964 
035 |a 3551528 
035 |a ocm42950440 
040 |a ZCU  |c ZCU  |d MdBJ  |d OrLoB-B 
040 |a ZCU  |c ZCU  |d NIC 
042 |a pcc 
049 |a JHEE 
050 4 |a TK7895.G36  |b I33 1999 
111 2 |a IEEE Symposium on FPGAs for Custom Computing Machines  |d (1999 :  |c Napa Valley, Calif.) 
245 1 0 |a Proceedings, Seventh annual IEEE Symposium on Field-Programmable Custom Computing Machines :  |b FCCM'99 : April 21-23, 1999, Napa Valley, California /  |c sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; edited by Kenneth L. Pocek and Jeffrey M. Arnold 
246 1 8 |a 1999 IEEE Symposium on Field-Programmable Custom Computing Machines 
246 3 |a Seventh annual IEEE Symposium on Field-Programmable Custom Computing Machines 
246 3 0 |a 1999 IEEE Symposium on Field-Programmable Custom Computing Machines 
246 3 0 |a 7th annual IEEE Symposium on Field-Programmable Custom Computing Machines  
246 3 0 |a FCCM'99 
246 3 0 |a Field-programmable custom computing machines 
246 3 0 |a IEEE Symposium on Field-Programmable Custom Computing Machines 
260 |a Los Alamitos, Calif. :  |b IEEE Computer Society,  |c c1999 
300 |a x, 319 p. :  |b ill. ;  |c 28 cm 
504 |a Includes bibliographical references and index 
505 0 0 |t Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System /  |r J. M. P. Cardoso and H. C. Neto --  |t CAD Suite for High-Performance FPGA Design /  |r B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson and M. Rytting --  |t Formal Verification of Reconfigurable Cores /  |r S. Singh and C. J. Lillieroth --  |t Transmutable Telecom System and Its Application /  |r T. Miyazaki, T. Murooka, M. Katayama and A. Takahara --  |t Implementation and Evaluation of a Prototype Reconfigurable Router /  |r J. R. Hess, D. C. Lee, S. J. Harper, M. T. Jones and P. M. Athanas --  |t Pipeline Vectorization for Reconfigurable Systems /  |r M. Weinhardt and W. Luk --  |t Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks /  |r M. B. Gokhale and J. M. Stone --  |t Parallelizing Applications into Silicon /  |r J. Babb, M. Rinard, C. A. Moritz, W. Lee, M. Frank, R. Barua and S. Amarasinghe --  |t Reconfigurable Elements for a Video Pipeline Processor /  |r M. R. Piacentino, G. S. van der Wal and M. W. Hansen --  |t ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator /  |r B. Kastrup, A. Bink and J. Hoogerbrugge --  |t CPR: A Configuration Profiling Tool /  |r S. Cadambi and S. C. Goldstein --  |t Debugging Techniques for Dynamically Reconfigurable Hardware /  |r N. McKay and S. Singh --  |t Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems /  |r M. Vasilko and D. Cabanis --  |t Reconfigurable Computing for Augmented Reality /  |r W. Luk, T. K. Lee, J. R. Rice, N. Shirazi and P. Y. K. Cheung --  |t Sepia: Scalable 3D Composing using PCI Pamette /  |r L. Moll, A. Heirich and M. Shand --  |t Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking /  |r Z. Luo, M. Martonosi and P. Ashar --  |t FAFNER - Accelerating Nesting Problems with FPGAs /  |r J. C. Alves, J. C. Ferreira, C. Albuquerque, J. F. Oliveira, J. S. Ferreira and J. Silva Matos --  |t Field Programmable Gate Array Based Radar Front-End Digital Signal Processing /  |r T. J. Moeller and D. R. Martinez --  |t Optimizing FPGA-Based Vector Product Designs /  |r D. Benyamin, W. Luk and J. Villasenor --  |t PCI-PipeRench and SwordAPI: A System for Stream-based Reconfigurable Computing /  |r R. Laufer, R. R. Taylor and H. Schmit --  |t Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor /  |r A. A. Chien and J. H. Byun --  |t Implementing an API for Distributed Adaptive Computing Systems /  |r M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, P. Athanas and B. Schott --  |t Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms /  |r G. Orlando and C. Paar --  |t Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping /  |r M. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng and P. H. W. Leong --  |t Dynamic Precision Management for Loop Computations on Reconfigurable Architectures /  |r K. Bondalapati and V. K. Prasanna --  |t Accelerating Run-Time Reconfiguration on FCCMs /  |r J.-P. Heron and R. F. Woods --  |t Virtual Hardware Handler for RTR Systems /  |r R. Turner, R. F. Woods, S. Sezer and J.-P. Heron --  |t Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results /  |r E. K. Pauer, P. D. Fiore and J. M. Smith --  |t Development System for FPGA-Based Digital Circuits /  |r V. Sklyarov, J. Fonseca, R. Monteira, A. Oliveira, A. Melo, N. Lau, I. Skliarova, P. Neves and A. Ferrari --  |t Design of JTAG Based Run Time Reconfigurable System /  |r C. Cousineau, F. Laperle and Y. Savaria --  |t Architectures for System-Level Applications of Adaptive Computing /  |r B. Schott, C. Chen, S. Crago, J. Czarnaski, M. French, I. Hom, T. Tho and T. Valenti --  |t Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures /  |r V. Srinivasan and R. Vemuri --  |t Enabling Automatic Module Generation for FCCM Compilers /  |r A. Koch --  |t ICARUS: A Dynamically Reconfigurable Computer Architecture /  |r M. Baxter --  |t SONIC - A Plug-In Architecture for Video Processing /  |r S. D. Haynes, P. Y. K. Cheung, W. Luk and J. Stone --  |t Reconfigurable Platform for Academic Purposes /  |r C. Teuscher, J.-O. Haenni, F. J. Gomez, H. F. Restrepo and E. Sanchez --  |t VHDL Placement Directives for Parametric IP Blocks /  |r J. Hwang, C. Patterson and S. Mitra --  |t Runlength Compression Techniques for FPGA Configurations /  |r S. Hauck and W. D. Wilson --  |t Accelerating An IR Automatic Target Recognition Application with FPGAs /  |r J. Jean, X. Liang, B. Drozd and K. Tomko --  |t Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware /  |r B. Levine, S. Natarajan, C. Tan, D. Newport and D. Bouldin --  |t Hybrid Data/Configuration Caching for Striped FPGAs /  |r D. Deshpande, A. K. Somani and A. Tyagi --  |t On Reconfiguring Cache for Computing /  |r H.-S. Kim, A. K. Somani and A. Tyagi --  |t Reconfigurable Pipelines in VLIW Execution Units /  |r R. D. Williams and B. D. Kuebert --  |t Fast Online Placement for Reconfigurable Computing Systems /  |r K. Bazargan and M. Sarrafzadeh --  |t Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor /  |r L. Gao, S. Shrivastava, H. Lee and G. E. Sobelman --  |t Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware /  |r M. Abramovici and J. T. de Sousa --  |t Reducing Compilation Time of Zhong's FPGA-based SAT solver /  |r P. K. Chan, M. J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu and M. Zhu --  |t FPGA-based Structures for On-line FFT and DCT /  |r D. Lau, A. Schneider, M. D. Ercegovac and J. Villasenor --  |t FPGA-based Fan Beam Image Reconstruction Module /  |r L. Maltar, F. M. G. Franca, V. C. Alves and C. L. Amorim --  |t Bezier Curve Rendering on Virtex /  |r D. MacVicar, S. Singh and R. Slous 
650 0 |a Computer engineering  |v Congresses 
650 0 |a Field programmable gate arrays  |v Congresses 
650 7 |a Computer engineering  |2 fast 
650 7 |a Field programmable gate arrays  |2 fast 
655 7 |a Conference papers and proceedings  |2 fast 
700 1 |a Arnold, Jeffrey M 
700 1 |a Pocek, Kenneth L 
710 2 |a IEEE Computer Society  |b Technical Committee on Computer Architecture. 
999 1 0 |i 945072af-391f-486f-9a60-55f7a1e9d460  |l 991013186429707861  |s US-MDBJ  |m proceedings_seventh_annual_ieee_symposium_on_field_programmable_custom_____1999_______ieeeca________________________________________ieee_symposium_on_fp_______________p 
999 1 0 |i 945072af-391f-486f-9a60-55f7a1e9d460  |l 3551528  |s US-NIC  |m proceedings_seventh_annual_ieee_symposium_on_field_programmable_custom_____1999_______ieeeca________________________________________ieee_symposium_on_fp_______________p 
999 1 1 |l 991013186429707861  |s ISIL:US-MDBJ  |t BKS  |a LSC shmoffs  |b 31151018104418  |c TK7895.G36 I33 1999 QUARTO  |d 0  |x jhbooks  |y 23360122260007861  |p LOANABLE 
999 1 1 |l 3551528  |s ISIL:US-NIC  |t BKS  |a engr,anx  |b 31924070130335  |c TK7895.G36 I22 1999  |d lc  |k 1  |x Book  |y e0b9b1dd-ea6c-4af1-9c43-d5408f73647b  |p LOANABLE 

Similar Items