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|t Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System /
|r J. M. P. Cardoso and H. C. Neto --
|t CAD Suite for High-Performance FPGA Design /
|r B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson and M. Rytting --
|t Formal Verification of Reconfigurable Cores /
|r S. Singh and C. J. Lillieroth --
|t Transmutable Telecom System and Its Application /
|r T. Miyazaki, T. Murooka, M. Katayama and A. Takahara --
|t Implementation and Evaluation of a Prototype Reconfigurable Router /
|r J. R. Hess, D. C. Lee, S. J. Harper, M. T. Jones and P. M. Athanas --
|t Pipeline Vectorization for Reconfigurable Systems /
|r M. Weinhardt and W. Luk --
|t Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks /
|r M. B. Gokhale and J. M. Stone --
|t Parallelizing Applications into Silicon /
|r J. Babb, M. Rinard, C. A. Moritz, W. Lee, M. Frank, R. Barua and S. Amarasinghe --
|t Reconfigurable Elements for a Video Pipeline Processor /
|r M. R. Piacentino, G. S. van der Wal and M. W. Hansen --
|t ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator /
|r B. Kastrup, A. Bink and J. Hoogerbrugge --
|t CPR: A Configuration Profiling Tool /
|r S. Cadambi and S. C. Goldstein --
|t Debugging Techniques for Dynamically Reconfigurable Hardware /
|r N. McKay and S. Singh --
|t Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems /
|r M. Vasilko and D. Cabanis --
|t Reconfigurable Computing for Augmented Reality /
|r W. Luk, T. K. Lee, J. R. Rice, N. Shirazi and P. Y. K. Cheung --
|t Sepia: Scalable 3D Composing using PCI Pamette /
|r L. Moll, A. Heirich and M. Shand --
|t Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking /
|r Z. Luo, M. Martonosi and P. Ashar --
|t FAFNER - Accelerating Nesting Problems with FPGAs /
|r J. C. Alves, J. C. Ferreira, C. Albuquerque, J. F. Oliveira, J. S. Ferreira and J. Silva Matos --
|t Field Programmable Gate Array Based Radar Front-End Digital Signal Processing /
|r T. J. Moeller and D. R. Martinez --
|t Optimizing FPGA-Based Vector Product Designs /
|r D. Benyamin, W. Luk and J. Villasenor --
|t PCI-PipeRench and SwordAPI: A System for Stream-based Reconfigurable Computing /
|r R. Laufer, R. R. Taylor and H. Schmit --
|t Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor /
|r A. A. Chien and J. H. Byun --
|t Implementing an API for Distributed Adaptive Computing Systems /
|r M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, P. Athanas and B. Schott --
|t Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms /
|r G. Orlando and C. Paar --
|t Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping /
|r M. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng and P. H. W. Leong --
|t Dynamic Precision Management for Loop Computations on Reconfigurable Architectures /
|r K. Bondalapati and V. K. Prasanna --
|t Accelerating Run-Time Reconfiguration on FCCMs /
|r J.-P. Heron and R. F. Woods --
|t Virtual Hardware Handler for RTR Systems /
|r R. Turner, R. F. Woods, S. Sezer and J.-P. Heron --
|t Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results /
|r E. K. Pauer, P. D. Fiore and J. M. Smith --
|t Development System for FPGA-Based Digital Circuits /
|r V. Sklyarov, J. Fonseca, R. Monteira, A. Oliveira, A. Melo, N. Lau, I. Skliarova, P. Neves and A. Ferrari --
|t Design of JTAG Based Run Time Reconfigurable System /
|r C. Cousineau, F. Laperle and Y. Savaria --
|t Architectures for System-Level Applications of Adaptive Computing /
|r B. Schott, C. Chen, S. Crago, J. Czarnaski, M. French, I. Hom, T. Tho and T. Valenti --
|t Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures /
|r V. Srinivasan and R. Vemuri --
|t Enabling Automatic Module Generation for FCCM Compilers /
|r A. Koch --
|t ICARUS: A Dynamically Reconfigurable Computer Architecture /
|r M. Baxter --
|t SONIC - A Plug-In Architecture for Video Processing /
|r S. D. Haynes, P. Y. K. Cheung, W. Luk and J. Stone --
|t Reconfigurable Platform for Academic Purposes /
|r C. Teuscher, J.-O. Haenni, F. J. Gomez, H. F. Restrepo and E. Sanchez --
|t VHDL Placement Directives for Parametric IP Blocks /
|r J. Hwang, C. Patterson and S. Mitra --
|t Runlength Compression Techniques for FPGA Configurations /
|r S. Hauck and W. D. Wilson --
|t Accelerating An IR Automatic Target Recognition Application with FPGAs /
|r J. Jean, X. Liang, B. Drozd and K. Tomko --
|t Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware /
|r B. Levine, S. Natarajan, C. Tan, D. Newport and D. Bouldin --
|t Hybrid Data/Configuration Caching for Striped FPGAs /
|r D. Deshpande, A. K. Somani and A. Tyagi --
|t On Reconfiguring Cache for Computing /
|r H.-S. Kim, A. K. Somani and A. Tyagi --
|t Reconfigurable Pipelines in VLIW Execution Units /
|r R. D. Williams and B. D. Kuebert --
|t Fast Online Placement for Reconfigurable Computing Systems /
|r K. Bazargan and M. Sarrafzadeh --
|t Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor /
|r L. Gao, S. Shrivastava, H. Lee and G. E. Sobelman --
|t Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware /
|r M. Abramovici and J. T. de Sousa --
|t Reducing Compilation Time of Zhong's FPGA-based SAT solver /
|r P. K. Chan, M. J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu and M. Zhu --
|t FPGA-based Structures for On-line FFT and DCT /
|r D. Lau, A. Schneider, M. D. Ercegovac and J. Villasenor --
|t FPGA-based Fan Beam Image Reconstruction Module /
|r L. Maltar, F. M. G. Franca, V. C. Alves and C. L. Amorim --
|t Bezier Curve Rendering on Virtex /
|r D. MacVicar, S. Singh and R. Slous
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