Proceedings, Seventh annual IEEE Symposium on Field-Programmable Custom Computing Machines : FCCM'99 : April 21-23, 1999, Napa Valley, California /
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| Other Authors: | , |
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Los Alamitos, Calif. :
IEEE Computer Society,
c1999
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| Subjects: |
Table of Contents:
- Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System / J. M. P. Cardoso and H. C. Neto
- CAD Suite for High-Performance FPGA Design / B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson and M. Rytting
- Formal Verification of Reconfigurable Cores / S. Singh and C. J. Lillieroth
- Transmutable Telecom System and Its Application / T. Miyazaki, T. Murooka, M. Katayama and A. Takahara
- Implementation and Evaluation of a Prototype Reconfigurable Router / J. R. Hess, D. C. Lee, S. J. Harper, M. T. Jones and P. M. Athanas
- Pipeline Vectorization for Reconfigurable Systems / M. Weinhardt and W. Luk
- Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks / M. B. Gokhale and J. M. Stone
- Parallelizing Applications into Silicon / J. Babb, M. Rinard, C. A. Moritz, W. Lee, M. Frank, R. Barua and S. Amarasinghe
- Reconfigurable Elements for a Video Pipeline Processor / M. R. Piacentino, G. S. van der Wal and M. W. Hansen
- ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator / B. Kastrup, A. Bink and J. Hoogerbrugge
- CPR: A Configuration Profiling Tool / S. Cadambi and S. C. Goldstein
- Debugging Techniques for Dynamically Reconfigurable Hardware / N. McKay and S. Singh
- Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems / M. Vasilko and D. Cabanis
- Reconfigurable Computing for Augmented Reality / W. Luk, T. K. Lee, J. R. Rice, N. Shirazi and P. Y. K. Cheung
- Sepia: Scalable 3D Composing using PCI Pamette / L. Moll, A. Heirich and M. Shand
- Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking / Z. Luo, M. Martonosi and P. Ashar
- FAFNER - Accelerating Nesting Problems with FPGAs / J. C. Alves, J. C. Ferreira, C. Albuquerque, J. F. Oliveira, J. S. Ferreira and J. Silva Matos
- Field Programmable Gate Array Based Radar Front-End Digital Signal Processing / T. J. Moeller and D. R. Martinez
- Optimizing FPGA-Based Vector Product Designs / D. Benyamin, W. Luk and J. Villasenor
- PCI-PipeRench and SwordAPI: A System for Stream-based Reconfigurable Computing / R. Laufer, R. R. Taylor and H. Schmit
- Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor / A. A. Chien and J. H. Byun
- Implementing an API for Distributed Adaptive Computing Systems / M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, P. Athanas and B. Schott
- Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms / G. Orlando and C. Paar
- Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping / M. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng and P. H. W. Leong
- Dynamic Precision Management for Loop Computations on Reconfigurable Architectures / K. Bondalapati and V. K. Prasanna
- Accelerating Run-Time Reconfiguration on FCCMs / J.-P. Heron and R. F. Woods
- Virtual Hardware Handler for RTR Systems / R. Turner, R. F. Woods, S. Sezer and J.-P. Heron
- Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results / E. K. Pauer, P. D. Fiore and J. M. Smith
- Development System for FPGA-Based Digital Circuits / V. Sklyarov, J. Fonseca, R. Monteira, A. Oliveira, A. Melo, N. Lau, I. Skliarova, P. Neves and A. Ferrari
- Design of JTAG Based Run Time Reconfigurable System / C. Cousineau, F. Laperle and Y. Savaria
- Architectures for System-Level Applications of Adaptive Computing / B. Schott, C. Chen, S. Crago, J. Czarnaski, M. French, I. Hom, T. Tho and T. Valenti
- Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures / V. Srinivasan and R. Vemuri
- Enabling Automatic Module Generation for FCCM Compilers / A. Koch
- ICARUS: A Dynamically Reconfigurable Computer Architecture / M. Baxter
- SONIC - A Plug-In Architecture for Video Processing / S. D. Haynes, P. Y. K. Cheung, W. Luk and J. Stone
- Reconfigurable Platform for Academic Purposes / C. Teuscher, J.-O. Haenni, F. J. Gomez, H. F. Restrepo and E. Sanchez
- VHDL Placement Directives for Parametric IP Blocks / J. Hwang, C. Patterson and S. Mitra
- Runlength Compression Techniques for FPGA Configurations / S. Hauck and W. D. Wilson
- Accelerating An IR Automatic Target Recognition Application with FPGAs / J. Jean, X. Liang, B. Drozd and K. Tomko
- Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware / B. Levine, S. Natarajan, C. Tan, D. Newport and D. Bouldin
- Hybrid Data/Configuration Caching for Striped FPGAs / D. Deshpande, A. K. Somani and A. Tyagi
- On Reconfiguring Cache for Computing / H.-S. Kim, A. K. Somani and A. Tyagi
- Reconfigurable Pipelines in VLIW Execution Units / R. D. Williams and B. D. Kuebert
- Fast Online Placement for Reconfigurable Computing Systems / K. Bazargan and M. Sarrafzadeh
- Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor / L. Gao, S. Shrivastava, H. Lee and G. E. Sobelman
- Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware / M. Abramovici and J. T. de Sousa
- Reducing Compilation Time of Zhong's FPGA-based SAT solver / P. K. Chan, M. J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu and M. Zhu
- FPGA-based Structures for On-line FFT and DCT / D. Lau, A. Schneider, M. D. Ercegovac and J. Villasenor
- FPGA-based Fan Beam Image Reconstruction Module / L. Maltar, F. M. G. Franca, V. C. Alves and C. L. Amorim
- Bezier Curve Rendering on Virtex / D. MacVicar, S. Singh and R. Slous