Digital System Verification : A Combined Formal Methods and Simulation Framework /
Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates...
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| Format: | Book |
| Language: | English |
| Published: |
Cham :
Springer International Publishing : Imprint: Springer,
2010
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| Edition: | 1st ed. 2010 |
| Series: | Synthesis Lectures on Digital Circuits & Systems,
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| Subjects: |
Internet
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| Call Number: |
ISIL:US-NCD |
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